1. Field of the Invention
The present invention relates to the field of semiconductor production in integrated circuits, and, more particularly, to the formation of gate insulation layers of transistor devices.
2. Description of the Related Art
The manufacturing process of integrated circuits (ICs) involves the fabrication of numerous semiconductor devices, such as field effect transistors, on a single substrate. In order to provide increased integration density and improved device performance, for instance with respect to signal processing time and power consumption, feature sizes of the semiconductor devices are steadily decreasing. In general, decreasing feature sizes of a field effect transistor provide a variety of advantages, such as high package density and small rise and fall times during switching of the transistors, due to, for example, a reduced channel length. On the other hand, steadily reducing the feature sizes of field effect transistors may lead to certain disadvantages that may significantly deteriorate the signal performance of the devices.
One of the problems involved in reducing feature sizes in a transistor is an increased gate leakage current of the final transistor device. As is well known, in a typical MOS device, a drain region and a source region are separated by a channel region, the conductivity of which is controlled by a voltage applied to a gate electrode that is formed above the channel region and electrically isolated therefrom by a thin gate insulation layer, e.g., a thin layer of silicon dioxide. Since the thickness of the insulation layer as well as the length of the channel has steadily been reduced, whereas the external voltages applied to the gate, drain and source regions have substantially been maintained, a relatively strong electric field acts on the charge carriers in the channel, drain and source regions. The large electric field may allow a charge carrier to gather sufficient energy to penetrate the gate insulation layer, or even to reach the gate electrode. In the latter case, a parasitic gate current is generated, while in the former case accumulation of charge carriers may occur, significantly affecting the characteristics of the device, which may result in an increase of the gate threshold voltage. Both effects may considerably reduce the switching speed of the transistor and may, furthermore, lead to a degraded long-term stability and a reduced reliability of the device. Although lightly doped drain and source regions are formed in an MOS transistor adjacent to the gate insulation layer for reducing the peak electric field, further measures are typically taken in an effort to weaken the effects described above. In a typical MOS process, a further oxidation step during the formation of a gate insulation layer comprised of silicon dioxide is commonly carried out to increase the thickness of the gate insulation layer at the edges adjacent to the source and drain regions, respectively.
To clearly demonstrate the problems involved with the formation of a gate oxide layer in a typical MOS transistor device, a typical prior art process flow will be described with reference to FIGS. 1(a) to 1(c). As the skilled person will readily appreciate, the figures depicting the prior art process flow are merely of schematic nature and transitions and boundaries illustrated as sharp lines may not be imparted as sharp transitions in a real device. Furthermore, the description of the typical prior art process refers to standard manufacturing procedures without specifying typical process parameter values used for these procedures, since individual processing steps may be accordingly adapted to meet specific design requirements. Moreover, only the relevant portions are illustrated and described.
FIG. 1(a) shows a schematic cross-sectional view of a portion of a typical MOS transistor device at a specific manufacturing stage. Over a semiconductor substrate 101 a gate electrode 102 in an initial manufacturing stage is formed and electrically isolated from the substrate 101 by a gate insulation layer 103 comprised of silicon dioxide. The process for forming the structure shown in FIG. 1(a) is well known. First, a layer of silicon dioxide is thermally grown on the substrate 101, and thereafter a layer of gate electrode material, such as polysilicon, is deposited on the silicon dioxide layer. Next, the polysilicon layer is patterned by photolithography and etching to form the gate electrode 102 depicted in FIG. 1(a).
FIG. 1(b) shows a schematic cross-sectional view of the device depicted in FIG. 1(a) wherein edges 104 of the gate oxide layer 103 have an increased thickness. FIG. 1(c) schematically shows a cross-sectional view of the device of FIG. 1(b) with a drain region 105 and a source region 106 formed in the substrate 101. As can be seen from the figures, the gate insulation layer 103 comprises the edges 104 adjacent to the drain region 105 and the source region 106, respectively, that extend with a substantially uniform thickness distribution along a transistor width dimension, which is the direction normal to the drawing plane of FIGS. 1(a) to 1(c). The increased thickness of the edges 104, in combination with the lightly doped portions of the drain region and the source region adjacent to the gate insulation layer 103, result in a reduced effective electric field. Accordingly, charge carrier accumulation and/or gate leakage currents are reduced. The formation of the edges 104 with an increased thickness requires, however, an additional oxidation step that leads to an additional high temperature treatment, thereby creating additional thermal stress in the substrate. Moreover, it is very difficult to control the shape of the insulation layer 103, i.e., the thickness distribution of the insulation layer 103, so that the final shape of the oxide layer is only adjustable within a small thickness range.
In view of the above, there exists a need for an improved method of forming a gate insulation layer on a semiconductor surface wherein the thickness distribution is adaptable to specific design requirements. Moreover, a need exists for an improved method of forming a gate insulation layer of an MOS transistor as well as for an MOS transistor device having an improved gate insulation layer.
According to one aspect of the present invention, a method of forming an oxide layer on a semiconductor layer comprises providing a substrate with the semiconductor layer, the semiconductor layer having a surface, depositing a mask layer with a predefined thickness over the semiconductor layer, forming an opening in the mask layer by patterning the mask layer so as to expose a portion of the surface of the semiconductor layer, the portion substantially coinciding with an area where the oxide layer is to be formed, performing an ion implantation step with a tilt angle with respect to a direction perpendicular to the exposed portion, thereby using the mask layer as an implantation mask so as to create an inhomogeneous or non-uniform ion concentration in the area of the exposed portion, and oxidizing the substrate to form the oxide layer, wherein a thickness of the oxide layer in a region of increased ion concentration is reduced due to a reduced oxidation rate.
According to the first aspect of the present invention, an oxide layer can be formed on a semiconductor layer, such as silicon, by a single oxidation step, wherein the thickness distribution of the oxide layer may be varied in conformity with design requirements. The oxidation rate significantly depends on the ion concentration deposited in and on the semiconductor layer. Thus, by controlling the ion concentration within the exposed portion of the semiconductor layer, the final thickness of the final oxide layer is determined by the distribution of the ions during the implantation step. Since the ions are directed in a substantially parallel manner at a selected tilt angle with respect to the surface, the ion concentration may easily be controlled by appropriately choosing the predefined thickness and/or the tilt angle.
According to further variations of the present invention, the tilt angle may be varied during the implantation step by, for example, rotating the substrate and/or two or more implantation steps may subsequently be performed, wherein the tilt angle is changed in each implantation step so as to obtain the ion concentration required for forming the oxide layer in conformity with specific design rules.
According to another aspect of the present invention, a method of forming a gate electrode in a field effect transistor comprises providing a substrate including a semiconductor region having a surface, depositing a mask layer with a predefined thickness over the semiconductor region and forming an opening with a length dimension and a width dimension in the mask layer to expose an area of the semiconductor region in which the gate electrode is to be formed. The method further comprises performing an ion implantation step to create an ion concentration that varies along the length dimension but is substantially uniform along the width dimension, oxidizing the exposed area to generate an oxide layer with a thickness depending on the ion concentration, depositing a layer of gate electrode material over the substrate to fill the opening, polishing the layer of gate electrode material to planarize a surface of the filled opening and removing the mask layer to form the gate electrode having the gate oxide layer with a thickness that varies in accordance with the ion concentration.
Contrary to the prior art process flow, the present invention allows to form a gate oxide layer in a single oxidation step, wherein the thickness of the oxide layer along the transistor length dimension can be adjusted to be in conformity with design requirements, since the implantation step involved can be well controlled.
Moreover, according to the present invention the thickness of the gate oxide layer may be adjusted so that the edges of the oxide layer extending along the transistor width dimension exhibit a thickness that is optimized for operation parameters of the final transistor, for example a specified maximum gate voltage and maximum drain source voltage of the transistor during operation.
According to still another aspect of the present invention, a field effect transistor formed on a substrate comprises: a drain region and a source region, formed in an active region, spaced apart from each other in a transistor length dimension and extending along a transistor width dimension in a substantially parallel manner, and a gate electrode formed over the active region and electrically insulated therefrom by a gate insulation layer, the gate insulation layer comprising an oxide having a thickness that varies along the transistor length dimension, but is substantially uniform along the transistor width dimension, wherein the thickness of the gate insulation layer adjacent to the source region is less than the thickness adjacent to the drain region.
The field effect transistor formed in accordance with the present invention comprises a gate insulation layer having an oxide portion the thickness of which is less at the source region than at the drain region. Since generally a thin gate insulation layer is desirable for improving performance of the transistor device, increasing the thickness of the gate insulation layer is preferably carried out at those locations where the highest electric field prevails so as to reduce charge carrier accumulation and parasitic gate leakage currents as previously explained. Accordingly, the present invention provides a field effect transistor comprising an asymmetric gate insulation layer thickness that insures optimal signal performance due to the gate insulation layer""s increased portion of small thickness compared to a symmetric prior art device while simultaneously significantly reducing charge carrier accumulation and parasitic gate leakage currents.